1. Field of the Invention
The present invention relates to the improvement of D/A converters which convert digital data into analog data.
2. Description of the Related Art
FIG. 4 shows an example of a conventional D/A converter. A resistor train 10 is composed of n pieces of resistors R.sub.1, R.sub.2, . . . R.sub.n connected in series to each other. One end of the resistor train 10 is connected to a power source node X and the other end is connected to an intermediate node P. Among connecting nodes of the resistors R.sub.1, R.sub.2, . . . R.sub.n, the intermediate node P and an output terminal Z and a ground node GND, resistors r.sub.1, r.sub.2, . . . r.sub.n and switch circuits S.sub.1, S.sub.2, . . . S.sub.n are connected. Further, between the intermediate node P and the ground node GND, a resistor r.sub.n+1 is connected.
All the resistors R.sub.1, R.sub.2, . . . R.sub.n have the same resistance value, R. All the resistors r.sub.1, r.sub.2, . . . r.sub.n, r.sub.n+1 have the same resistance value, 2R. These resistors comprise a well known ladder-type resistor circuit and a combined resistance of R.sub.2, R.sub.3, . . . R.sub.n and r.sub.1, r.sub.2, . . . r.sub.n, r.sub.n+1 is R.
A reference voltage is supplied to the power source node X and the ground voltage is supplied to the ground node GND. The output terminal Z is connected to, for instance, an operational amplifier and analog output data is obtained from an output of this operational amplifier.
Switch circuits S.sub.1, S.sub.2, . . . S.sub.n connect either one of the output terminal Z and the ground node GND to the power source node X. In FIG. 4, for instance, the switch circuit S.sub.1 connects the power source node X and the output terminal Z while the switch circuits S.sub.2, S.sub.3, . . . S.sub.n connect the power source node X and the ground node GND.
N-bit gate control signals D.sub.1, D.sub.2, . . . D.sub.n control the switch circuits S.sub.1, S.sub.2, . . . S.sub.n. The most significant bit (MSB) first bit D.sub.1 of the gate control signals is input to the switch circuit S.sub.1 and the least significant bit (LSB) D.sub.n is input to the switch circuit S.sub.n. Activating bits of the gate control signals bits changes over the switch circuits so that the power source node X and the output terminal Z are connected.
When voltage VX, which is not equal to ground voltage GND, is supplied to the power source node X, current IX (=VX/2R) flows to the resistor R.sub.1. A combined resistance of the resistors R.sub.2, R.sub.3, . . . R.sub.n and the resistors r.sub.1, r.sub.2, . . . r .sub.n, r.sub.n+1 is R and a resistance value of the resistor R.sub.1 is R, thus the current IX flows to the resistor R.sub.1.
This current IX is branched and flows to the resistor r.sub.1 and the resistor R.sub.2, respectively. The resistance of the resistor r.sub.1 (2R) is equal to the combined resistance of the resistors R.sub.2, R.sub.3, . . . R.sub.n and the resistors r.sub.2, r.sub.3, . . . r.sub.n, r.sub.n+1 (2R). So, the current IX/2 (=VX/4R) flows to both the resistors r.sub.1 and R.sub.2.
From a similar viewpoint, current IX/21, IX/22, . . . IX/2n flow to the resistors r.sub.1, r.sub.2, . . . r.sub.n. In other words the currents flowing to the resistors r.sub.1, r.sub.2, . . . r.sub.n are weighted by the power of 2.
Accordingly, because the power source node X and the output terminal Z are connected by the gate control signals D.sub.1, D.sub.2, . . . D.sub.n, weighted current flowing through the switches S.sub.1, S.sub.2, . . . S.sub.n can be taken out of the output terminal Z according to the gate control signals D.sub.1, D.sub.2, . . . D.sub.n. Thereafter, the digital-to-analog conversion is carried out by an operational amplifier connected to the output terminal Z.
However, the D/A converter described above has defects as shown below. First, since the resistors R.sub.1, R.sub.2, . . . R.sub.n and the resistors r.sub.1, r.sub.2, . . . r.sub.n, r.sub.n+1 are composed of polysilicon resistors or diffusion resistors, a chip area containing an applicable D/A converter will become large. Second, since the switch circuits S.sub.1, S.sub.2, . . . S.sub.n are composed of MOS transistors, the relation of resistance ratio among the resistors R.sub.1, R.sub.2, . . . R.sub.n and the resistors r.sub.1, r.sub.2, . . . r.sub.n, r.sub.n+1 is adversely affected by the ON resistance of the MOS transistors. Third, since voltage required for turning on/off the switch circuits S.sub.1, S.sub.2, . . . S.sub.n is large, it is disadvantageous for high-speed operation and for the characteristics of the converter resulting from deviations in the manufacturing process.
FIG. 5 shows another conventional D/A converter. In this D/A converter, the resistors R.sub.1, R.sub.2, . . . R.sub.n shown in FIG. 4 are substituted by N-channel MOS transistors T.sub.11, T.sub.12, T.sub.21, T.sub.22, . . . T.sub.n1, T.sub.n2, respectively and the resistors r.sub.1, r.sub.2, . . . r.sub.n and the switch circuits S.sub.1, S.sub.2, . . . S.sub.n shown in FIG. 4 are substituted by N-channel MOS transistors ST.sub.11, ST.sub.12, ST.sub.21, ST.sub.22, . . . ST.sub.n1, ST.sub.n2, respectively. Further, the resistor r.sub.n+1 is substituted by an N-channel MOS transistor ST.sub.n+1.
All the MOS transistors T.sub.11, T.sub.12, T.sub.21, T.sub.22, . . . T.sub.n1, T.sub.n2 ; ST.sub.11, ST.sub.12, ST.sub.21, ST.sub.22, . . . ST.sub.n1, ST.sub.n2 ; ST.sub.n+1 have the same conductive type and the same size (the driving force). Voltage VX that is applied to the power source node X is set at a value to operate all the MOS transistors in a non-saturated region.
The resistor R.sub.1 is composed of two MOS transistors T.sub.11, T.sub.12 which are connected in parallel with each other, the resistor R.sub.2 is composed of two MOS transistors T.sub.21, T.sub.22 which are connected in parallel with each other and, similarly, the resistor R.sub.n is composed of two MOS transistors T.sub.n1, T.sub.n2 which are connected in parallel with each other. And the gates of MOS transistors T.sub.11, T.sub.12, T.sub.21, T.sub.22, . . . T.sub.n1, T.sub.n2 are connected to a bias node which is supplied with voltage V.sub.DD.
The resistor r.sub.1 and the switch circuit S.sub.1 shown in FIG. 4 are composed of the MOS transistor ST.sub.11 connected to the output terminal Z and the MOS transistor ST.sub.12 connected to the ground node GND. And similarly, the resistor r.sub.n and the switch circuit S.sub.n shown in FIG. 4 are composed of the MOS transistor ST.sub.n1 connected to the output terminal Z and the MOS transistor ST.sub.n2 connected to the ground node GND.
A control signal C.sub.1 is applied to the gate of MOS transistor ST.sub.11 and a control signal C.sub.1 inverse is applied to the gate of MOS transistor ST.sub.12. Similarly, a control signal C.sub.n is applied to the gate of MOS transistor ST.sub.n1, and a control signal C.sub.n inverse is applied to the gate of MOS transistor ST.sub.n2.
N-channel MOS transistors were used above but P channel MOS transistors may be used instead of them.
On a D/A converter constructed as described above, assuming that voltage applied between the drain and source of each MOS transistor is V.sub.ds and gate voltage is Vb, the drain to source current Ids will be EQU I.sub.ds =K{2(Vb-Vt)V.sub.ds -V.sub.ds.sup.2 } (1) EQU K=(W/2L).(.epsilon..sub.si /t.sub.ox).mu.,
where W is a channel width, L is a channel length, .epsilon..sub.si is a dielectric constant of a gate insulator (silicon oxide layer), t.sub.ox is a thickness of a gate insulator, .mu. is the mobility of carriers in the channel and Vt is a voltage threshold of the MOS transistor.
According to the structure described above, it is possible to make a chip area small because the ON resistance of MOS transistors is used instead of the resistors from polysilicon and/or diffusion layers.
However, as can be seen from the above Equation (1), the current I.sub.ds has non-linearity as it contains the term V.sub.ds.sup.2. The variation of characteristics resulting from deviations in the manufacturing process becomes large. Further, since a large voltage is required to turn on/off the MOS transistors ST.sub.11, ST.sub.12, ST.sub.21, ST.sub.22, . . . ST.sub.n+1, it is disadvantageous for high speed operation.